Modern logic analog system design typically is based on software-implemented simulation methods conventionally referred to as so-called “bus simulation” or “channel simulation” where logic analog systems are mapped on equivalent electronic circuits basically known to those of skill in the art. See for instance High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices, John Wiley and Sons, 2000.
In order to illustrate channel simulation, reference is now made to FIG. 1 depicting a software-implemented equivalent circuit of a logic analog memory chip system, where each component is modeled to have specified electrical characteristics. For example, a logic analog memory chip system modeled as a channel as shown in FIG. 1 may comprise a memory controller 1, a motherboard 2, a plug 3, a printed circuit board 4, a memory chip package 5, and a memory chip 6 that are serially connected in that order by a data bus 8, as in typical built-in situations, where a packaged memory is connected to the printed circuit board that is plugged into the motherboard and controlled by the memory controller. More specifically, software-implemented channel simulation of the memory chip system maps electrical characteristics of each system component having a specifically designed physical (real) layout.
For testing electrical behavior of the model system, a bit pattern is generated, for instance using memory controller 1 or any other kind of bit pattern generator, which bit pattern is sent through the data bus (or channel) and is analyzed at the end of the channel using bit pattern analyzer 7 conductively connected to the memory chip 6 for determining a bit error rate as a result of comparing the generated bit pattern at the beginning of the channel and the analyzed bit pattern at the end of the channel.
As is known to those of skill in the art, electrical parasitics may occur at each modeled system component as a result of inductive, capacitive and/or resistive loads thereof that may effect a change of height and/or shape of transmitted bit pattern signals (i.e., distortion of transmitted bit pattern signals). Hence, degradation of the bit pattern signals may prevent a clear discrimination of logic values with accidental changes of logic values of the initial bit pattern sent through the channel.
Given a memory chip system as exemplified in FIG. 1, typically a problem occurs that the physical layout of the memory chip packaging has to be adapted separately to any specified physical memory chip system layout.
For further illustration thereof, reference is now made to FIG. 2 depicting a flow diagram of conventional development of the physical memory chip packaging layout in conventional channel simulation of memory chip systems. Typically, starting with forwarding of rough design input as to the desired chip package layout (giving information such as pin arrangement, pin density and the like) from memory system designers, package designers chose a specific package layout on basis of experience in line with the system designers' input. Package layout may eventually be adapted to the system designers' input. Next, the chosen package layout is further adapted to reduce electrical parasitics and is then supplied to the system designers for integration into the model memory system. Memory system designers then must check whether the electrical behavior of model system having integrated the suggested package layout satisfies their needs with respect to an achieved bit error rate. If so, the physical memory system including memory chip package is released and, if not, the process of developing packaging layout must be repeated to find an appropriately designed chip package. Typically, in developing the packaging layout, 15 to 20 iterations are necessary to find a packaging layout appropriately adapted to be integrated in a specific system layout. Consequently, development of the packaging layout can be very time consuming and cost consuming.
Furthermore, in recent years, density of system components, operational frequency, and bit rate of logic systems have increased tremendously so that the conventional approach to developing chip packages as described above is considered to be too slow and/or insufficient to cope with system developers needs.